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#pragma once

#include <vector>

#include "sim/queue.h"
#include "sm/instr_ptr.h"
#include "sm/warp.h"

namespace simtix {

namespace pipelined {

class FetchBuf {
 public:
  struct Entry {
    explicit Entry(uint32_t fetch_width)
        : instrs(fetch_width), bytes(fetch_width * 4) {}

    bool access_fault = false;     // True if an access fault occurred.
    bool ready = false;            // True if the entry is ready for processing.
    std::vector<InstrPtr> instrs;  // Pointer to the <Instr> object.
    std::vector<uint8_t> bytes;    // Raw bytes of the fetched instructions.
  };

  explicit FetchBuf(const PipelinedSM::Param &p);

  void Allocate(Warp *warp, uint64_t fetch_addr, std::optional<uint32_t> ssw);

  Entry *GetPendingFetchReq();

  void ServePendingFetchReq();

  Entry *GetPendingFetchResp();

  void ServePendingFetchResp();

  bool empty() const { return free_ids_.full(); }
  bool full() const { return free_ids_.empty(); }

 protected:
  std::vector<Entry> buf_;

  sim::SizedQueue<uint32_t> free_ids_;
  sim::SizedQueue<uint32_t> pending_req_ids_;
  sim::SizedQueue<uint32_t> pending_resp_ids_;
};

}  // namespace pipelined

}  // namespace simtix