Class simtix::uvm::FrontendGoldenImpl

ClassList > simtix > uvm > FrontendGoldenImpl

Inherits the following classes: simtix::pipelined::PipelinedSMImpl

Inherited by the following classes: simtix::uvm::FrontendGolden::Impl

Public Functions

Type	Name
	FrontendGoldenImpl (const std::string & name, uint32_t cid, const ArchParam & p=kDefaultArchParam, const PipelinedSM::Param & pp=PipelinedSM::kDefaultParam)
	~FrontendGoldenImpl ()

Public Functions inherited from simtix::pipelined::PipelinedSMImpl

See simtix::pipelined::PipelinedSMImpl

Type	Name
virtual void	AttachDMem (MemoryInterface * dmem) override Connect data memory interface (cache or main memory).
virtual void	AttachIMem (MemoryInterface * imem) override Connect instruction memory interface (cache or main memory).
	PipelinedSMImpl (const std::string & name, uint32_t cid, const ArchParam & p=kDefaultArchParam, const PipelinedSM::Param & pp=PipelinedSM::kDefaultParam) Constructor for PipelinedSMImpl .
virtual int	Process (const opencl::WorkGroup & wg) override Launch a workgroup on this SM.
virtual void	Reset () override Reset pipeline state and clear buffer.
virtual void	ResetStat () override Reset and create a new stat for a workgroup.
virtual BaseArbitrator *	arbitrator () override Get banked register arbitrator.
virtual BaseLoadStoreUnit *	lsu () override Get load-store unit interface.
virtual std::shared_ptr< BaseSMImpl::Stat >	stat () override Get Common stats for SMs.
virtual BaseSMImpl::WorkGroupStat *	wg_stat () override Get current workgroup stats for SMs.
	~PipelinedSMImpl ()

Public Functions inherited from simtix::BaseSMImpl

See simtix::BaseSMImpl

Type	Name
virtual void	AttachDMem (MemoryInterface * dmem) Connect data memory interface.
virtual void	AttachIMem (MemoryInterface * imem) Connect instruction memory interface.
	BaseSMImpl (const std::string & name, uint32_t cid, const ArchParam & p=kDefaultArchParam) Constructor for BaseSMImpl .
virtual int	NotifyBarrier (uint32_t wid, uint8_t bid, uint8_t wc) Notify the SM of a barrier instruction.
virtual void	NotifyCtrlFlowChange (uint32_t wid, bool is_diverged, uint64_t wpc, uint64_t sswpc) = 0 Notify the SM of a control flow change.
virtual void	NotifyException (uint32_t wid, uint64_t mcause, uint64_t mepc, uint64_t mtval) Notify the SM of an exception.
virtual int	Process (const opencl::WorkGroup & wg) Process a work-group and initialize all threads.
int32_t	ReadCSR (uint16_t addr, uint64_t * data) Read a Control and Status Register (CSR).
virtual void	Reset () Reset the SM to its initial state.
virtual void	ResetStat () Reset and create a new stat for a workgroup.
virtual BaseArbitrator *	arbitrator () = 0
virtual BaseLoadStoreUnit *	lsu () = 0
uint32_t	marchid () const
uint64_t	mcycle () const
const std::vector< uint64_t > &	minstrets ()
uint32_t	mvendorid () const
const std::string	name () const
uint32_t	num_active_warps () const
uint32_t	num_warps () const
uint32_t	num_warps_per_warpgroup () const
void	set_mcycle (uint64_t cycle)
virtual std::shared_ptr< Stat >	stat () = 0
const std::vector< std::unique_ptr< Warp > > &	warps () const
virtual WorkGroupStat *	wg_stat () = 0
uint32_t	xclgoffx () const
uint32_t	xclgoffy () const
uint32_t	xclgoffz () const
uint32_t	xclgsx () const
uint32_t	xclgsy () const
uint32_t	xclgsz () const
uint32_t	xclsx () const
uint32_t	xclsy () const
uint32_t	xclsz () const
uint32_t	xclwx () const
uint32_t	xclwy () const
uint32_t	xclwz () const
uint32_t	xdim () const
uint64_t	xkernelarg () const
uint64_t	xkernelpc () const
uint64_t	xmhartidbase () const
virtual	~BaseSMImpl ()

Protected Attributes

Type	Name
MockInstrBuffer *	mock_ibuffer_
std::deque< FrontendGolden::Input >	test_q_

Protected Attributes inherited from simtix::pipelined::PipelinedSMImpl

See simtix::pipelined::PipelinedSMImpl

Type	Name
CoalescingLoadStoreUnit	coalescing_lsu_
InstrQueue	commit_iq_
std::unique_ptr< CommitStage >	commit_stage_
std::shared_ptr< mem::CacheInterface >	dcache_
InstrQueue	decode_iq_
std::unique_ptr< DecodeStage >	decode_stage_
InstrQueue	execute_iq_
std::unique_ptr< ExecuteStage >	execute_stage_
FetchBuf	fetch_buf_
std::unique_ptr< FetchStage >	fetch_stage_
std::unique_ptr< InstrBuffer >	ibuffer_
std::shared_ptr< mem::CacheInterface >	icache_
const uint32_t	kCommitWidth
const uint32_t	kDecodeWidth
const uint32_t	kExecuteWidth
const uint32_t	kFetchWidth
const uint32_t	kOperandCollectWidth
const uint32_t	kScheduleWidth
const uint32_t	kThreadsPerWarp
const uint32_t	kWarpsPerCore
const uint32_t	kWarpsPerWarpGroup
std::unique_ptr< OperandCollectStage >	operand_collect_stage_
InstrQueue	operandcollect_iq_
std::unique_ptr< PCGenStage >	pc_gen_stage_
PipelinedArbitrator	pipelined_arbitrator_
InstrQueue	schedule_iq_
std::unique_ptr< ScheduleStage >	schedule_stage_
std::shared_ptr< BaseSMImpl::Stat >	stat_
std::shared_ptr< WorkGroupStat >	wg_stat_

Protected Attributes inherited from simtix::BaseSMImpl

See simtix::BaseSMImpl

Type	Name
std::vector< Barrier >	barriers_
uint32_t	cid_
MemoryInterface *	dmem_port_ = `nullptr`
BaseSM::FaultStatus	fault_status_ = `{0, 0, 0, 0}`
MemoryInterface *	imem_port_ = `nullptr`
uint32_t	marchid_ = `0`
uint64_t	mcycle_ = `0`
std::vector< uint64_t >	minstrets_
uint32_t	mvendorid_ = `0`
const std::string	name_
uint32_t	num_active_warps_ = `0`
const uint32_t	num_threads_per_warp_
const uint32_t	num_warps_
uint32_t	num_warps_per_warpgroup_ = `1`
std::unique_ptr< WarpSched >	scheduler_
BaseSM::Status	status_
std::vector< Warp * >	valid_leader_warps_
std::vector< std::unique_ptr< Warp > >	warps_
Barrier	wg_completion_barrier_
uint32_t	wg_serial_id_ = `0`
uint32_t	xclgoffx_ = `0`
uint32_t	xclgoffy_ = `0`
uint32_t	xclgoffz_ = `0`
uint32_t	xclgsx_ = `0`
uint32_t	xclgsy_ = `0`
uint32_t	xclgsz_ = `0`
uint32_t	xclsx_ = `0`
uint32_t	xclsy_ = `0`
uint32_t	xclsz_ = `0`
uint32_t	xclwx_ = `0`
uint32_t	xclwy_ = `0`
uint32_t	xclwz_ = `0`
uint32_t	xdim_ = `0`
uint64_t	xkernelarg_ = `0`
uint64_t	xkernelpc_ = `0`
uint64_t	xmhartidbase_ = `0`

Protected Functions

Type	Name
virtual void	Tick () override Advance pipeline by one cycle.

Protected Functions inherited from simtix::pipelined::PipelinedSMImpl

See simtix::pipelined::PipelinedSMImpl

Type	Name
void	ClearInstrQueue () Clear all instruction queues in pipeline.
virtual void	NotifyCtrlFlowChange (uint32_t wid, bool is_diverged, uint64_t wpc, uint64_t sswpc) override Handle control flow changes (branches/divergence).
virtual void	NotifyException (uint32_t wid, uint64_t mcause, uint64_t mepc, uint64_t mtval) override Notify exception from a warp.
virtual void	Tick () override Advance pipeline by one cycle.
bool	WarpAdditionalCheck (int wid, std::optional< uint32_t > ssw)

Protected Functions inherited from simtix::BaseSMImpl

See simtix::BaseSMImpl

Type	Name
bool	BarrierCompleted (const Barrier & b) const
virtual bool	IsBusy ()
virtual void	Tick () Advance pipeline by one cycle.

Public Functions Documentation

function FrontendGoldenImpl

explicit simtix::uvm::FrontendGoldenImpl::FrontendGoldenImpl (
    const std::string & name,
    uint32_t cid,
    const ArchParam & p=kDefaultArchParam,
    const PipelinedSM::Param & pp=PipelinedSM::kDefaultParam
)

function ~FrontendGoldenImpl

simtix::uvm::FrontendGoldenImpl::~FrontendGoldenImpl ()

Protected Attributes Documentation

variable mock_ibuffer_

MockInstrBuffer* simtix::uvm::FrontendGoldenImpl::mock_ibuffer_;

variable test_q_

std::deque<FrontendGolden::Input> simtix::uvm::FrontendGoldenImpl::test_q_;

Protected Functions Documentation

function Tick

Advance pipeline by one cycle.

virtual void simtix::uvm::FrontendGoldenImpl::Tick () override

This pipelined implementation will call each stage in reverse order to simulate hardware nonblocking behavior.

Implements simtix::pipelined::PipelinedSMImpl::Tick

The documentation for this class was generated from the following file projects/simtix/src/simtix/uvm/frontend_golden.h