Class Index

a

• ArchParam (simtix)
• ArchParamBuilder (simtix)
• AtomicArbitrator (simtix)
• AtomicLoadStoreUnit (simtix)
• AtomicSM (simtix)
• AtomicSMImpl (simtix)
• Average (simtix::stat::Vector)

b

• BankedMemory (simtix::mem)
• Barrier (simtix::BaseSMImpl)
• BaseArbitrator (simtix)
• BaseFunctionUnit (simtix)
• BaseLoadStoreUnit (simtix)
• BaseSM (simtix)
• BaseSMImpl (simtix)
• BaseSystem (simtix::system)

c

• Cache (simtix::mem)
• CacheImpl (simtix::mem)
• CacheInterface (simtix::mem)
• Clocked (simtix::sim)
• CoalescingLoadStoreUnit (simtix)
• CommitStage (simtix::pipelined)
• CompletionInfo (simtix::system::TaskDispatcher)
• Config (simtix::system::SingleCoreSystem)
• CoreRequest (simtix::CoalescingLoadStoreUnit)
• CoreRequest (simtix::mem::CacheImpl)

d

• DataArray (simtix::mem)
• DataArrayRequest (simtix::mem::CacheImpl)
• DecodeStage (simtix::pipelined)
• DelayQueue (simtix::sim)

e

• Entry (simtix::pipelined::FetchBuf)
• ExecuteStage (simtix::pipelined)

f

• FaultStatus (simtix::BaseSM)
• FcfsDelayQueue (simtix::sim)
• FetchBuf (simtix::pipelined)
• FetchFilterEntry (simtix::pipelined::PCGenStage)
• FetchStage (simtix::pipelined)
• FixedLatencyUnit (simtix)
• formatter< simtix::ArchParam::WarpSchedPolicies > (fmt)
• formatter< simtix::BaseSM::Status > (fmt)
• formatter< simtix::mem::Cache::Param::ReplacementPolicies > (fmt)
• formatter< simtix::mem::Cache::Param::WriteHitPolicies > (fmt)
• formatter< simtix::mem::Cache::Param::WriteMissPolicies > (fmt)
• formatter< simtix::mem::MemType > (fmt)
• formatter< simtix::SMType > (fmt)
• formatter< simtix::stat::Operation > (fmt)
• formatter< simtix::system::TaskDispatcher::CompletionInfo::Status > (fmt)
• formatter< simtix::system::TaskDispatcher::Status > (fmt)
• Formula (simtix::stat)
• FrontendGolden (simtix::uvm)
• FrontendGoldenImpl (simtix::uvm)

g

• GenericDelayQueue (simtix::sim)
• Group (simtix::stat)
• Gto (simtix)

i

• Impl (simtix::AtomicSM)
• Impl (simtix::mem::BankedMemory)
• Impl (simtix::mem::Cache)
• Impl (simtix::mem::NBHBCache)
• Impl (simtix::mem::SimpleMemory)
• Impl (simtix::mem::XBar)
• Impl (simtix::pipelined::PipelinedSM)
• Impl (simtix::system::TaskDispatcher)
• Impl (simtix::uvm::FrontendGolden)
• Input (simtix::uvm::FrontendGolden)
• Instr (simtix)
• InstrAuipc (simtix)
• InstrBranch (simtix)
• InstrBuffer (simtix::pipelined)
• InstrFormosa (simtix)
• InstrJal (simtix)
• InstrJalr (simtix)
• InstrLoad (simtix)
• InstrLui (simtix)
• InstrOp (simtix)
• InstrOp32 (simtix)
• InstrOpFp (simtix)
• InstrOpFused (simtix)
• InstrOpImm (simtix)
• InstrOpImm32 (simtix)
• InstrPool (simtix)
• InstrPoolInterface (simtix)
• InstrPtr (simtix)
• InstrQueue (simtix)
• InstrRetire (simtix::trace::KonataRetireReporter)
• InstrStore (simtix)
• InstrStream (simtix::pipelined::InstrBuffer)
• InstrSystem (simtix)
• InstrTrap (simtix)

k

• Kernel (simtix::opencl)
• KonataRetireReporter (simtix::trace)
• KonataTracer (simtix::trace)

l

• Lrr (simtix)

m

• Mem (simtix::system::SingleCoreSystem::Config)
• MemConfig
• MemoryInterface (simtix::mem)
• MemRequest (simtix::CoalescingLoadStoreUnit)
• MemResponse (simtix::mem::CacheImpl)
• MockInstrBuffer (simtix::uvm)
• MSHR (simtix::mem::MshrFile)
• MshrFile (simtix::mem)

n

• NBHBCache (simtix::mem)
• NBHBCacheImpl (simtix::mem)
• NonCacheableEntry (simtix::mem::Cache::Param)

o

• OperandCollectStage (simtix::pipelined)
• OstreamTracer (simtix::trace)
• Output (simtix::uvm::FrontendGolden)

p

• Param (simtix::pipelined::PipelinedSM)
• Param (simtix::mem::BankedMemory)
• Param (simtix::mem::Cache)
• Param (simtix::mem::SimpleMemory)
• ParamBuilder (simtix::pipelined::PipelinedSM)
• Payload (simtix::mem::MemoryInterface)
• PCGenStage (simtix::pipelined)
• PipelinedArbitrator (simtix)
• PipelinedSM (simtix::pipelined)
• PipelinedSMImpl (simtix::pipelined)
• PostfixExpr (simtix::stat)

r

• Reduction (simtix::stat::Vector)
• Rep (simtix::mem::TagArray)
• Request (simtix::AtomicLoadStoreUnit)
• Request (simtix::PipelinedArbitrator)
• Request (simtix::mem::SimpleMemory::Impl)
• RRWarpSched (simtix)

s

• Scalar (simtix::stat)
• ScalarBase (simtix::stat)
• ScheduleStage (simtix::pipelined)
• SimConfig
• SimpleMemory (simtix::mem)
• SingleCoreSystem (simtix::system)
• SingleCoreSystemStat (simtix::system::SingleCoreSystem)
• SizedQueue (simtix::sim)
• slave_t (simtix::mem::XBar::Impl)
• Stat (simtix::AtomicSMImpl)
• Stat (simtix::BaseSMImpl)
• Stat (simtix::PipelinedArbitrator)
• Stat (simtix::WarpSched)
• Stat (simtix::mem::BankedMemory::Impl)
• Stat (simtix::mem::CacheImpl)
• Stat (simtix::mem::NBHBCacheImpl)
• Stat (simtix::pipelined::PipelinedSMImpl)
• StatBase (simtix::stat)
• Sum (simtix::stat::Vector)

t

• Tag (simtix::mem::TagArray)
• TagArray (simtix::mem)
• TaskDispatcher (simtix::system)
• TaskDispatcherImpl (simtix::system)
• Testbed (tb)
• TestbedStat
• Thread (simtix)

v

• Vector (simtix::stat)

w

• Warp (simtix)
• WarpSched (simtix)
• WorkGroup (simtix::opencl)
• WorkGroupStat (simtix::AtomicSMImpl)
• WorkGroupStat (simtix::BaseSMImpl)
• WorkGroupStat (simtix::pipelined::PipelinedSMImpl)
• WriteBufferEntry (simtix::mem::CacheImpl)

x

• XBar (simtix::mem)