Class List

Here are the classes, structs, unions and interfaces with brief descriptions:

• struct MemConfig
• struct SimConfig
• namespace fmt
  • struct formatter< simtix::ArchParam::WarpSchedPolicies >
  • struct formatter< simtix::BaseSM::Status >
  • struct formatter< simtix::SMType >
  • struct formatter< simtix::mem::Cache::Param::ReplacementPolicies >
  • struct formatter< simtix::mem::Cache::Param::WriteHitPolicies >
  • struct formatter< simtix::mem::Cache::Param::WriteMissPolicies >
  • struct formatter< simtix::mem::MemType >
  • struct formatter< simtix::stat::Operation >
  • struct formatter< simtix::system::TaskDispatcher::CompletionInfo::Status >
  • struct formatter< simtix::system::TaskDispatcher::Status >
• namespace simtix
  • class ArchParam
  • class ArchParamBuilder
  • class AtomicArbitrator
  • class AtomicLoadStoreUnit
    • struct Request
  • class AtomicSM
    • class Impl
  • class AtomicSMImpl
    • struct Stat
    • struct WorkGroupStat
  • class BaseArbitrator
  • class BaseFunctionUnit
  • class BaseLoadStoreUnit
  • class BaseSM Base class for all Streaming Multiprocessor (SM) implementations.
    • struct FaultStatus
  • class BaseSMImpl Base class for the Streaming Multiprocessor (SM) implementation.
    • struct Barrier
    • struct Stat
    • struct WorkGroupStat
  • class CoalescingLoadStoreUnit
    • struct CoreRequest
    • struct MemRequest
  • class FixedLatencyUnit
  • class Gto
  • class Instr Base class for all different kinds of Instructions.
  • class InstrAuipc InstrAuipc handles the operations for instruction with AUIPC opcode.
  • class InstrBranch InstrBranch handles the operations for instruction with BRANCH opcode.
  • class InstrFormosa InstrFormosa handles the operations for CUSTOM-1 opcode instructions.
  • class InstrJal InstrJal class handles the operations for instruction with JAL opcode.
  • class InstrJalr InstrJalr handles the operations for instruction with JALR opcode.
  • class InstrLoad InstrLoad handles the operations for instruction with LOAD opcode.
  • class InstrLui InstrLui handles the operations for instruction with LUI opcode.
  • class InstrOp InstrOp class handles the operations for instruction with OP opcode.
  • class InstrOp32 InstrOp32 class handles the operations for OP-32 opcode instructions.
  • class InstrOpFp
  • class InstrOpFused
  • class InstrOpImm InstrOpImm handles the operations for instructions with OP-IMM opcode.
  • class InstrOpImm32 InstrOpImm32 handles the operations for OP-IMM-32 opcode instructions.
  • class InstrPool InstrPool manages the allocation and recycling of instruction objects.
  • class InstrPoolInterface Interface class for different <Instr> type of pool.
  • class InstrPtr Pointer to the <Instr> object.
  • class InstrQueue InstrQueue is a SizedQueue containingInstrPtr .
  • class InstrStore InstrStore handles the operations for instruction with STORE opcode.
  • class InstrSystem InstrSystem class handles the operations for instruction with SYSTEM.
  • class InstrTrap template class for RISC-V exception code.
  • class Lrr
  • class PipelinedArbitrator
    • struct Request
    • struct Stat
  • class RRWarpSched
  • class Thread Class for thread.
  • class Warp Class for warp.
  • class WarpSched
    • struct Stat
  • namespace mem
    • class BankedMemory A banked memory implementation.
      • class Impl
        • struct Stat
      • struct Param
    • class Cache A cache implementation.
      • class Impl
      • struct Param
        • struct NonCacheableEntry
    • class CacheImpl
      • struct CoreRequest
      • struct DataArrayRequest
      • struct MemResponse
      • struct Stat
      • struct WriteBufferEntry
    • class CacheInterface Abstract interface for cache implementations.
    • class DataArray
    • class MemoryInterface An abstract class for all objects that have a read/write memory interface.
      • struct Payload
    • class MshrFile
      • struct MSHR
    • class NBHBCache Non-blocking high-bandwidth cache implementation.
      • class Impl
    • class NBHBCacheImpl
      • struct Stat
    • class SimpleMemory A simple memory implementation with fixed latency.
      • class Impl
        • struct Request
      • struct Param
    • class TagArray
      • struct Rep
      • struct Tag
    • class XBar Crossbar for connecting multiple memory interfaces.
      • class Impl
        • struct slave_t
  • namespace opencl
    • struct Kernel
    • struct WorkGroup
  • namespace pipelined
    • class CommitStage Commit the instruction.
    • class DecodeStage Decode the instruction.
    • class ExecuteStage Execute the instruction.
    • class FetchBuf Implement a buffer for fetching instructions.
      • struct Entry Represent a single fetch buffer entry containing fetched instructions and control data.
    • class FetchStage Handle the instruction fetch.
    • class InstrBuffer A instruction buffer.
      • struct InstrStream Represent the instruction stream for a single warp.
    • class OperandCollectStage Collect operand from banked register file.
    • class PCGenStage Fetch request generation stage.
      • struct FetchFilterEntry
    • class PipelinedSM
      • class Impl Internal implementation wrapper for public PipelinedSM interface.
      • class Param
      • class ParamBuilder
    • class PipelinedSMImpl Integrate all stages to construct the pipelined SM implementation.
      • struct Stat
      • struct WorkGroupStat
    • class ScheduleStage Schedule the warp.
  • namespace riscv
  • namespace sim
    • class Clocked Abstract base class for tick-driven simulation objects.
    • class DelayQueue
    • class FcfsDelayQueue
    • class GenericDelayQueue
    • class SizedQueue
  • namespace stat
    • class Formula
    • class Group
    • class PostfixExpr
    • class Scalar
    • class ScalarBase
    • class StatBase All visible stat objects will inherit this base class.
    • class Vector
      • class Average
      • class Reduction
      • class Sum
  • namespace system
    • class BaseSystem Base class for all system implementations.
    • class SingleCoreSystem
      • struct Config
        • struct Mem
      • struct SingleCoreSystemStat
    • class TaskDispatcher Task dispatcher for managing workgroups and SMs.
      • struct CompletionInfo
      • class Impl
    • class TaskDispatcherImpl
  • namespace trace
    • class KonataRetireReporter
      • struct InstrRetire
    • class KonataTracer Dump Konata traces to a given std::ostream. This class is a singleton class and only one instance will exist in a program. Users should dump the trace with <KONATA>.
    • class OstreamTracer Dump traces to a given std::ostream. This class is a singleton class and only one instance will exist in a program. Users should dump the trace with <DDUMP> or <DPRINTF>.
  • namespace utils
  • namespace uvm
    • class FrontendGolden
      • class Impl
      • struct Input
      • struct Output
    • class FrontendGoldenImpl
    • class MockInstrBuffer
• namespace std
• namespace tb
  • class Testbed
• struct TestbedStat